1. Field of the Invention
The present invention is directed to a frequency divider and more particularly, to a frequency divider having a pulse duty factor of 1:1 at an odd dividing ratio.
2. Description of the Related Art
Clock signals of different frequency are frequently needed for clocking modern digital circuits. Such clock signals are generally derived from a reference clock signal by dividing its clock frequency. Depending on the dividing ratio, clock signals of quite different frequency can be generated in this manner.
The frequency of a clock signal is frequently divided by means of a clock pulse counter which is incremented by the pulses of the clock signal to be divided in order to be reset periodically when a predetermined final count has been reached in each case. A divided output clock signal can be formed, for example from the most significant bit of the current count. The frequency of the output clock signal is then lower than the frequency of the clock signal to be divided, by the factor of the final count.
The problem with this type of frequency division is, however, that with odd dividing ratios, the pulse duty factor of the divided output clock signal is not equal to 1:1. In this connection, the pulse duty factor is the ratio between the period of time in which the output clock signal is at a logic 1 level and the period of time in which the output clock signal is at a logic 0 level. However, many applications require an output clock signal with a pulse duty factor of 1:1. The deviation of the pulse duty factor of an output clock signal generated by means of the method described above deviates very greatly from the ideal value of 1:1, especially in the case of small odd dividing ratios such as 3 or 5.
It is the object of the present invention to specify a method for dividing the frequency of a clock signal by means of which an output clock signal having a predetermined pulse duty factor can be generated. In particular, it should be possible to generate an output clock signal having a pulse duty factor of 1:1 even at an odd dividing ratio. It is also the object of the invention to specify a frequency divider circuit for implementing the method according to the invention.
The above objects are achieved by a method including counting clock pulses of the clock signal by a clock pulse counter; alternating between resetting the clock pulse counter after passing through a first count different and resetting the clock pulse counter after passing through a different second count difference; forming a first signal, the logic state of which is changed by a rising clock signal edge when the clock pulse counter has a predetermined first count; forming a second signal, the logic state of which is changed by a falling clock signal edge when the clock pulse counter has a predetermined second count; and generating a divided output clock signal by a logical operation on the first signal and the second signal. The above objects are also achieved by a frequency divider circuit including storing a predetermined counter end value in a read/write register; and resetting the clock pulse counter as determined by a comparison of a current count of the clock pulse counter with the counter end value stored in the read/write register.
Dividing the frequency of a clock signal in accordance with the invention is done with the aid of a clock pulse counter counting the clock pulses of the clock signal, which counter which alternately runs through a first count difference, called A in the text which follows, and a different second count difference, called B in the text which follows. In this connection, count difference is the respective number of counted clock pulses after which the clock pulse counter is reset in each case. A respective count difference thus corresponds to the difference between a respective counter start value to which the clock pulse counter is reset, and a respective counter end value after which, when it has been reached, the clock pulse counter is reset again. Alternately running through different count differences can be achieved, for example, by alternately resetting the clock pulse counter to different counter start values from one counter end value which remains the same, or by resetting the clock pulse counter after different counter end values have alternately been reached, the counter start value remaining the same.
Using the clock pulse counter, a first signal and a second signal are formed, the logic state (0 or 1) of which is changed when a first or second count, in each case predetermined, of the clock pulse counter is present. A change in the state of the first signal is triggered by a risingEdge of the clock signal whilst a change in the state of the second signal is initiated by a falling clock signal edge. Since a logical initial state is assumed again after two successive state changes in both signals, the signal period of both signals is A+B clock periods in the simplest case, i.e. when the counter passes alternately through the first and the second count difference. From the first and the second signal, a divided output clock signal is derived by logically combining these signals. The output clock signal thus also exhibits a period of A+B clock periods. The dividing ratio of a clock frequency division according to the invention, i.e. the ratio between the period of the output clock signal and the clock period of the clock signal, is thus A+B in the aforementioned case.
The pulse duty factor of the output clock signal can be adjusted within wide limits by selecting the in each case predetermined count at which the first and, respectively, second signal changes its logic state and by selecting the logical combination of the first and second signal. In particular, a pulse duty factor of 1:1 can also be achieved with odd dividing ratios in a simple manner. This can be achieved, for example, by selecting B=A+1 resulting in an odd dividing ratio of A+B=2A+1 and by selecting both the first and the second predetermined count to be equal to the counter end value. The first and the second signal thus change their logic state during the same clock period and are thus offset in time with respect to one another by half a clock period. In the case where the first and the second signal are set to the logic state of 1 after the counter passes through the greater count difference B=A+1 in each case, and to the logic state of 0 after the counter passes through the smaller count difference A, an output clock signal having a pulse duty factor of 1:1 can be formed by a logical OR operation on the first and the second signal. If, in contrast, the first and second signal are set to 0 after the counter has passed through the greater count difference B=A+1, and to 1 after it has passed through the smaller count difference A, an output clock signal having a pulse duty factor of 1:1 can be formed by a logical AND operation on the first and the second signal.
According to an advantageous further development of the invention, a read/write register can be provided in which a predetermined counter end value and/or a predetermined counter start value and/or a predetermined first and/or second count can be stored. The dividing ratio and the pulse duty factor of the output clock signal of an existing frequency divider circuit according to the invention can thus be varied in a particularly simple manner by changing the register content.
These together with other objects and advantages which will be subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals refer to like parts throughout.